Equalizer/forward error correction automatic mode selector

ABSTRACT

An apparatus for automatically selecting one of a standard decision directed mode and a soft dd mode in a decision feedback equalizer for receiving a data signal includes an equalizer utilizing forward error correction for providing first and second output signals corresponding to a DFE automatic switching mode and a soft automatic switching mode, respectively, and a comparator for comparing byte error rates of the first and second output signals for selecting as a superior mode that mode associated with a lower ByER and outputting the output signal with the lower ByER. A lock detector provides a lock signal derived from the DFE output signal with the lower ByER and a mode switch selectively places the DFE outputs in one of the dd modes or a blind mode, depending on the lock signal.

This application claims the benefit, under 35 U.S.C. § 365 ofInternational Application PCT/US03/11207, filed Apr. 10, 2003, which waspublished in accordance with PCT Article 21(2) on Oct. 30, 2003 inEnglish and which claims the benefit of U.S. Provisional PatentApplication No. 60/373,205, filed Apr. 17, 2002.

Reference is also hereby made to copending U.S. Provisional PatentApplication No. 60/372,970, entitled ARCHITECTURE FOR A DECISIONFEEDBACK EQUALIZER and filed in the names of the present inventors Heo,Markman, Park and Gelfand on Apr. 16, 2002 and whereof the benefit ofpriority is hereby claimed and whereof the disclosure is hereinincorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to adaptive equalizers, whichmay be used to compensate for signal transmission by way of a channelhaving unknown and/or time-varying characteristics such as may occur inhigh definition television reception and, more particularly, relates toan equalizer/forward error correction (FEC) automatic mode selector.

2. Background of the Invention

In the Advanced Television Systems Committee (ATSC) standard for HighDefinition Television (HDTV) in the United States, the equalizer is anadaptive filter which receives a data stream transmitted by vestigialsideband modulation (VSB), VSB being the modulation system in accordancewith the ATSC-HDTV standard, at an average rate equal to the symbol rateof approximately 10.76 MHz. The equalizer attempts to remove or reducelinear distortions mainly caused by multipath propagation, which are atypical characteristic of the terrestrial broadcast channel. See UnitedStates Advanced Television Systems Committee, “ATSC Digital TelevisionStandard,” Sep. 16, 1995.

Decision Feedback Equalizers (DFE's) as used in the communications artgenerally include a feedforward filter (FFF) and a feedback filter(FBF), wherein typically the FBF is driven by decisions on the output ofthe signal detector, and the filter coefficients can be adjusted toadapt to the desired characteristics to reduce the undesired distortioneffects. Adaptation may typically take place by transmission of a“training sequence” during a synchronization interval in the signal orit may be by a “blind algorithm” using property restoral techniques ofthe transmitted signal. Typically, the equalizer has a certain number oftaps in each of its filters, depending on such factors as the multipathdelay spread to be equalized, and where the tap spacings “T” aregenerally, but not always, at the symbol rate. An important parameter ofsuch filters is the convergence rate, which may be defined as the numberof iterations required for convergence to an optimum setting of theequalizer. For a more detailed analysis and discussion of suchequalizers, algorithms used, and their application to communicationswork, reference is made to the technical literature and to text-bookssuch as, for example, “Digital Communications”, by John G. Proakis,2^(nd) edition, McGraw-Hill, New York, 1989; “Wireless Communications”by Theodore S. Rappaport, Prentice Hall PTR, Saddle River, N.J., 1996;and “Principles of Data Transmission” by A. P. Clark, 2^(nd) edition,John Wiley & Sons, New York, 1983.

BRIEF SUMMARY OF THE INVENTION

In accordance with principles of the present invention, mode selectorapparatus automatically selects one of a standard automatic switchingmode and a soft automatic switching mode in a decision feedbackequalizer. The mode selector apparatus is adapted for use in a datasignal processing system with equalization and includes an equalizerwhich provides first and second DFE outputs corresponding to a standarddd mode and a soft dd mode, respectively; and a comparator whichcompares byte error rates (ByER) of the first and second DFE outputs,selects as a superior mode that mode associated with a lower ByER andoutputs the DFE output with the lower ByER.

BRIEF DESCRIPTION OF THE DRAWING

The invention will be more fully understood from the detaileddescription which follows, in conjunction with the drawings, in which

FIG. 1 shows a schematic block diagram of a decision feedback equalizer(DFE) architecture;

FIG. 2 shows bit error rate (BER) versus signal to noise ratio (SNR) indB for an equalizer and Viterbi decoder in the additive white Gaussiannoise (AWGN) channel;

FIG. 3 shows equalizer lock detector output in the AWGN channel andautomatic switching mode for different values of SNR;

FIG. 4 shows bit error rate (BER) versus signal to noise ratio (SNR) indB for an equalizer and Viterbi decoder under a 3 dB, 3 microsecond (μs)ghost signal and additive white Gaussian noise (AWGN);

FIG. 5 shows the number of burst errors versus burst size at theequalizer output for blind and automatic switching mode and differentSNR measures;

FIG. 6 shows an equalizer lock detector output in the −3 dB, 3 μs plusAWGN channel for different values of SNR;

FIG. 7 shows an embodiment of an equalizer/forward error correction(FEC) automatic mode selector in accordance with the present invention;and

FIG. 8 shows a compare and select unit flow chart in accordance with thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

An equalizer/forward error correction (FEC) automatic mode selectorequalizer in accordance with the present invention comprises a T-spaced(where T is the symbol period) DFE (Decision Feedback) equalizer withthree available modes: training, blind and decision directed (dd).

Before entering into a detailed description of preferred embodiments ofthe present invention, it will be helpful to a better understanding ofthe principles of the present invention and to defining certain terms toconsider first a somewhat simplified block diagram of a DecisionFeedback Equalizer (DFE) architecture as shown in FIG. 1.

The input to the DFE is coupled to a Feed-Forward Filter (FFF) 10 whoseoutput is coupled to a summation unit 12, the other input to summationunit 12 being coupled to the output of a Feed-Back Filter (FBF) 14. Theoutput of summation unit 12 is coupled to a slicer 16, to an input of amode switch 18, and to a lock detector 20. The output of lock detector20 is coupled to a control input of mode switch 18. The output of slicer16 is coupled to another input of mode switch 18 and an output of modeswitch 18 is coupled to an input of FBF 14. Another output of modeswitch 18 is coupled to coefficient control inputs of FFF 10 and FBF 14.

The functions of the FFF 10, FBF 14 and slicer 16 are well known andconstitute the basic functions of filtering and quantization,respectively. See, for example, the afore-cited text by Proakis.Additional information on filters and their implementation can be foundin various textbooks such as, for example, “Digital Signal Processing,”by John G. Proakis and Dimitris G. Manolakis, Prentice Hall, New Jersey;1996 and “Introduction to Digital Signal Processing,” by Roman Kuc,McGraw-Hill Book Company, New York; 1988. Lock detector 20 isresponsible for the equalizer convergence detection function. It updatesthe lock detector output by comparing the equalizer output against theslicer levels with a threshold. If the equalizer output and slicerlevels are within the threshold distance, a lock or convergence isdetected. Mode switch 18 selects the input to the FBF filter as well asthe error and control signals to be used in the equalizer adaptation,according to the equalizer mode of choice. It also checks the lockdetector output. In normal operation, mode switch 18 has an automaticswitching capability, which depends on the output of equalizer lockdetector 20. Mode switch 18 interprets the training and blind modes asbeing used for convergence purposes only. After the equalizer lockdetector detects convergence, the equalizer is then transitioned to thedecision directed (dd) mode. If convergence is lost, the equalizer goesback to training or blind mode.

In the Advanced Television Systems Committee (ATSC) standard, a trainingsequence was included in the field sync to allow for initial 1 equalizerconvergence. In training mode, the equalizer coefficients are onlyupdated during the field sync. However, two main drawbacks associatedwith its use are that it requires prior correct detection of the fieldsync and that the training sequence is contained in the field sync,which only occurs approximately every 25 milliseconds (ms), possiblyresulting in slow convergence.

For ghost environments that make it difficult to detect a field sync orwith a dynamic component, it is of interest to have an initialadjustment of the equalizer tap coefficients independent of a trainingsequence, that is, self-recovering or blind. See, for example the abovecited text by Proakis and the paper by D. N. Godard, “Self-RecoveringEqualization and Carrier Tracking in Two Dimensional Data CommunicationSystems” IEEE Trans. on Commun., Vol. COM-28, pp. 1867–1875, November1980.

Furthermore, because it works on every data symbol, the blind algorithmwill have a faster convergence.

As is typically the case in the conventional dd mode, the input to FBF14 is the output of slicer 16. Thus, in the dd mode, the adaptationerror and the input to the feedback filter are aided by the presence ofa slicer, and coefficient adaptation takes place throughout the datasequence. This mode does not have good convergence capabilities, butafter convergence, it has advantages over the other two modes. Theadvantage of dd mode with respect to blind mode is attributable to thepresence of the slicer, resulting in better MSE (mean squared error) andBER (bit error rate) performance at the equalizer output. With respectto the training mode, the fact that dd updates its tap on every symbol,as opposed to training symbols only, allows for faster adaptation andtracking capabilities.

It is herein recognized that the use of blind and dd modes as an aid oras alternative approaches to the training mode are desirable because,inter alia, the training mode in the ATSC-HDTV standard has a slowconvergence, as well as poor dynamic tracking capabilities.

In what follows, reference is made to an HDTV receiver and to some ofits components and it may be helpful to briefly mention their context.In such a receiver, the adaptive channel equalizer is typically followedby a phase tracking network for removing phase and gain noise from whichthe signal goes to a trellis decoder followed by a data de-interleaver.The signal is then Reed-Solomon error corrected and then descrambledafter which it undergoes audio, video, and display processing. Furtherdetails may be found in the technical literature such as, for example,the handbook “Digital Television Fundamentals”, by Michael Robin andMichel Poulin, McGraw-Hill, New York; second edition, 2000.

FIG. 2 shows a graph of BER (Bit Error Rate) vs. SNR (Signal-to-NoiseRatio) performance curves for the equalizer and Viterbi decoder of anHDTV receiver in the AWGN (Additive White Gaussian Noise) channel. Theperformance is measured after the equalizer as well as after the Viterbidecoder (VD). The Viterbi decoder follows the equalizer in the receiverdesign and decodes the first level of FEC (Forward Error Correction),corresponding to a TCM (Trellis Coded Modulation) code.

In FIG. 2, three curves are shown for the equalizer (upper set ofcurves) as well as VD output (lower set of curves): one for theequalizer in blind mode only, the second for the equalizer in automaticswitching mode and the third for the equalizer in soft automaticswitching mode. In automatic switching mode, the equalizer is in blindmode prior to convergence, and switches to dd mode after convergence isdetected. If convergence is lost, it switches back to blind mode. Softautomatic switching mode is similar to automatic switching mode, exceptthat the dd mode is a soft dd mode. In soft dd mode, the input to thefeedback filter is the output of the equalizer, instead of the sliceroutput.

In view of the characteristics shown in FIG. 2, the following are hereinrecognized:

-   -   (a) The equalizer output performance under automatic mode is        equal to or better than under blind mode. For increasing SNR,        the automatic switching performance is increasingly better;    -   (b) The VD output performance reflects the equalizer output        performance. Under automatic switching mode, it is equal or        better than under blind mode. For increasing SNR, the automatic        switching performance is increasingly better.    -   (c) The automatic switching and soft automatic switching modes        present similar performance both at the equalizer output and VD        output.

It is helpful to a better understanding of the relationship betweenblind and dd mode in automatic switching mode to consider FIG. 3, whichshows curves of the equalizer lock detector in the AWGN channel fordifferent SNR values. The SNR is 13 dB in the top graph of FIG. 3, 15 dBin the center, and 18 dB in the bottom graph. In FIG. 3, a 0 level onthe ordinate scale indicates that the equalizer is not locked, that is,it is in blind mode. When the equalizer is locked, the lock detectoroutput assumes the value of 1, that is, the equalizer is in dd mode. Weobserve that for low SNR, the equalizer is mainly in blind mode, thatis, convergence is never detected due to the high level of noise. Thisis an imperfection of the lock detector that generally cannotpracticably be overcome. For high SNR, the convergence is eventuallydetected, and the equalizer is transitioned to dd mode. At a medium SNR,there is constant switching of the lock detector, with noise affectingits ability to detect equalizer convergence besides potentiallyaffecting the equalizer convergence. Similar behavior can be expectedfor the equalizer in soft automatic switching mode.

If a multipath signal is now introduced in the channel, some differencesin the system simulation may be observed. FIG. 4 shows BER vs. SNRperformance curves for the HDTV receiver in the AWGN plus multipathchannel. The multipath channel comprises one 3 dB, 3 μsec ghost, whichis a relatively strong ghost. As in FIG. 2, the performance is measuredafter the equalizer (upper set of curves) as well as after the Viterbidecoder (VD) (lower set of curves). Also, three curves are shown for theequalizer as well as for the VD output: one for the equalizer in blindmode only, another for the equalizer in automatic switching mode and thethird one for the equalizer in soft automatic switching mode.

In soft automatic switching mode, the equalizer is in blind mode priorto convergence, and switches to soft dd mode after convergence isdetected. If convergence is lost, it switches back to blind mode. Insoft dd mode, as opposed to the conventional dd mode, the input to thefeedback filter is the output of the equalizer.

In view of the characteristics shown in FIG. 4, the following are hereinrecognized:

(a) Under automatic switching mode the equalizer output performance isequal to or better than in blind mode and in soft automatic switchingmode. For increasing SNR, the automatic switching performance isincreasingly better.

(b) However, the VD output performance does not reflect the equalizeroutput performance, especially for medium SNR. For those values of SNR,the VD output performance is worse under automatic switching mode ratherthan in blind mode and soft automatic switching mode by up to about 1.5dB.

While it is not apparent from FIG. 4, additional simulations show thatfor higher SNR values, the VD performance under automatic switching modewill again be better or equal than under blind mode and soft automaticswitching mode.

Additional simulations also show that the problem described in item babove becomes more evident for strong ghosts, although still present ata smaller scale for weaker ghosts.

It is helpful to an understanding of the difference in performancebehavior between the equalizer and Viterbi decoder when the equalizer isunder blind or automatic switching mode, to compute the number of errorbursts at the equalizer output under these two modes.

FIG. 5 shows plots for the number of bursts of errors versus the lengthof the burst under both equalizer modes, and for different SNR measures.The SNR is 18 dB in the top graph of FIG. 5, 21 dB in the center, and 25dB in the bottom graph. In view of the characteristics shown in FIG. 5,the following are herein recognized:

Under low SNR conditions, the number of errors is very similar for bothblind and automatic switching mode. Long error bursts are present inboth modes, with a slightly greater number for blind mode;

Under medium SNR conditions, the number of error bursts and error burstlength are clearly greater for automatic switching mode as compared withblind mode, as the number of long error bursts under blind modedecreases and automatic switching mode is not affected as much by theincrease in SNR; and

Under high SNR conditions the number of error bursts and error burstlength become greater for blind mode as compared with automaticswitching mode, as the number of long error bursts under automaticswitching mode now decreases at a faster rate with increasing SNR.

FIG. 6 shows the equalizer lock detector output against the number ofiterations (×10⁴). The SNR is 18 dB in the top graph of FIG. 6, 21 dB inthe center, and 25 dB in the bottom graph. The notion of low, medium orhigh SNR is actually dependent on the ghost profile and strength, sincedifferent ghosts imply different performance. However, as shown in FIG.6, there is a relation between the SNR and the equalizer lock detectorperformance. As was the case in the AWGN channel, it is observed thatfor low SNR, the equalizer is mainly in blind mode, that is, convergenceis never detected due to the high level of noise. For high SNR, theconvergence is eventually detected, and the equalizer is transitioned todd mode, remaining stable in that mode. At medium SNR, there is constantswitching of the lock detector, as the level of noise does not allow fora stable dd mode. Similar behavior can be expected for the equalizer insoft automatic switching mode.

Based on the foregoing considerations and information presented, it is afeature of the present invention to detect these conditions of errorpropagation for which the standard dd mode delivers a worse performancethan the soft dd mode, and to switch the modes. In accordance with theprinciples of the present invention, the choice of the proper mode isbased on the BER at the output of the receiver. In this way, thereceiver only switches with certainty, and avoids making the error forchannel environments where the soft dd mode would actually deliver aworse performance. Such results were not observed in the presentsimulations, though this does not a guarantee that this will be the casefor all channels.

FIG. 7 shows in block diagram form an exemplary embodiment of anequalizer/forward error correction automatic mode selector in accordancewith the present invention, as applied to a HDTV receiver by way ofexample. FIG. 7 includes the Forward Error Correction (FEC) section ofthe receiver.

In FIG. 7, a block 30 includes the equalizer, associated filters,slicer, and lock detector(s), as hereinbefore described and explained.Block 30 provides an equalizer output (1) representing automaticswitching output to a forward error correction unit 32, indicated as FEC1. Block 30 also provides an equalizer output (0) representing softautomatic switching to a further forward error correction unit 34,indicated as FEC 0. Block 30 may also include the phase tracking networkfollowing the equalizer, or jointly designed with the equalizer as anequalizer/phase tracker unit. The outputs of forward error correctionunits 32 and 34 are fed to a Compare & Select unit 36, which providesthe decoded bit output signal. Compare & Select unit 36 also provides aselect signal sel to an equalizer mode switch 38. Mode switch 38 iscoupled to receive both equalizer outputs (0) and (1) and for exchangingsignals with block 30, as will hereinafter be explained in detail.

In accordance with an aspect of the invention, the FEC section of thereceiver is duplicated and the output of the equalizer is delivered fortwo separate modes: automatic switching and soft automatic switching.The two separate equalizer outputs can be obtained in different ways:

(a) By also duplicating the equalizer hardware; and

(b) By a concurrent output equalizer design which permits concurrentoutputs as, for example, the equalizer described in the afore-mentionedcopending U.S. Provisional Patent Application Ser. No. 60/372,970,entitled DECISION FEEDBACK EQUALIZER, whereof the entire disclosure hasbeen herein incorporated by reference and to which reference is made fora more detailed description.

As disclosed and described in the above-cited provisional patentapplication, a decision feedback equalizer for processing a data signalprovides concurrent equalizer outputs for hard decision directed andsoft decision directed modes. The difference between the hard and softdd modes is associated with the input to the equalizer feedback filterbeing the output of the slicer (hard decision) or equalizer output (softdecision). The joint architecture takes advantage of the fact that foreach equalizer output symbol soft decision bit representation, a subsetof these bits corresponds to the hard decision representation. As aresult, the equalizer permits the concurrent output of two distinctmodes with essentially the same hardware as a one output equalizer.

In FIG. 7, the equalizer filters, slicer and lock detector are asdescribed hereinabove. The equalizer mode switch is also similar to thatdescribed above, except that it receives a control signal from theCompare & Select unit. This control signal, sel, identifies which of thetwo modes (automatic switching or soft automatic switching) has a betterperformance. It only needs to be fed back to the equalizer mode switchunit in item (b) above for the case of a single equalizer architecture.In this case, it determines which output should be used by the equalizerlock detector to identify a lock condition.

When there is one equalizer with concurrent outputs, one in (hard)automatic switching mode and another in soft automatic switching mode,there is only one lock detector. The Compare & Select unit chooses thebest performance system and outputs it. It also feeds back a selectorsignal to the equalizer mode switch. This selector indicates the bestperformance system and is used by the lock detector to decide which ofthe two outputs to check. This selector can also be used to choose whichof the two concurrent outputs is fed to the equalizer slicer in order tocreate the adaptation error as well as choosing which of the FBFcoefficient adaptation equations is used in the concurrent outputequalizer. As stated above, this equalizer may advantageously utilizethe equalizer design described in the afore-mentioned copending U.S.Provisional Patent Application entitled DECISION FEEDBACK EQUALIZER.

In item (a) above, for a dual equalizer architecture, there are twoequalizers, and each is a separate entity with a separate lock detector.One equalizer is in (hard) automatic switching mode and the other insoft automatic switching mode. The equalizer mode switch thusessentially comprises two separate systems. In addition to checking thesignal sel, the equalizer mode switch also checks on the lock detectoroutput to decide whether the equalizer mode should be blind or (soft)dd. The Compare & Select unit chooses the best performance system andoutputs it. No feedback is needed.

The FEC section of the receiver includes the following blocks: ViterbiDecoder (VD), de-interleaver and Reed-Solomon (RS) decoder. In theory,it needs to be duplicated into FEC0 and FEC1, as shown in FIG. 7.However, in general, the RS decoder works at a smaller rate than thesymbol rate, since it operates on symbols of several bits. In this case,each RS symbol is a byte, and the rate is slow enough such that the RSdecoder hardware can be shared between the two FEC blocks. In addition,the de-interleaver control performs the same operation in both blocksand can be shared. Therefore, the de-interleaver may have the samecontrol as before and twice the memory, where each portion of the memoryis equally addressed by the control. It is herein recognized that onecould also share VD control sections between the two FEC sections;however, since the VD for the ATSC-HDTV standard is actually a set of 12interleaved decoders, it is simpler to duplicate the entire unit.

Additional blocks present in the receiver include the derandomizer andthe output interface, which need only be included following the Compare& Select unit, but could also be considered part of each FEC unit.

Each FEC section outputs three signals, namely: the output bit, the byteerror count at the output of the RS decoder (bec) and the uncorrectedsegment count at the output of the RS decoder (usc). The bec signalrepresents the number of byte errors that have been corrected by the RSdecoder over a specified window W total number of bytes. The usc signalrepresents the number of uncorrected segments over a specified window Wtotal number of bytes. In a RS decoder, bec and usc are related to theBER and can be used to estimate the BER. The function of the Compare &Select unit is to compare the bec counts for the two FEC units, every Wbytes, or equivalently the usc count.

The Compare & Select unit is an additional element of the Equalizer/FECmode selector. It basically subtracts bec1 and bec2 and compares itagainst a threshold Thr. If the absolute value of the subtraction s isbelow the threshold, then both equalizer outputs are performing atbasically the same level, and the correct output is established as theoutput of unit 0. This output corresponds to the equalizer being set inthe automatic switching mode (blind plus dd modes). As a result, thevariable set is set to 0, and is fed back to the mode switch to identifythe equalizer output 0 as the output on which the equalizer lockdetector should operate.

On the other hand, if IsI is greater than or equal to Thr, then bothequalizer outputs are performing at different levels. The algorithm thencompares bec0 and bec1 and chooses the smaller as the best performance.If s is greater than 0, then bec0 is greater than bec1, the output bitis set to output bit 1, and sel is set to 1 to identify the equalizeroutput 1 as the output on which the equalizer lock detector shouldoperate. Correspondingly, if s is smaller than or equal to 0, then theoutput bit 0 is chosen and sel is set to 0. The entire operation of theCompare & Select unit is then repeated for every W bytes. A similardesign can be analogously implemented for the usc count.

FIG. 8 shows a Compare & Select unit flowchart for a bec comparison, thesymbols used being as defined above.

The equalizer/FEC automatic mode selector has been illustrativelydescribed as being designed for the HDTV-ATSC equalizer; however, itsprinciples in accordance with the invention can be applied to anygeneral equalizer with a DFE architecture, in a system where theequalizer is followed by a Trellis or convolutional decoder. For such asystem, the error propagation into the DFE filter originated by lineardistortion, noise and the slicer presence in dd mode results in burstytype of noise at the equalizer output, which will tend to impair thedecoder performance. In addition, although described in the context of asymbol-spaced (T-spaced, where T is the symbol period) equalizer, theinvention can also be applied to fractionally spaced equalizers.Fractionally spaced equalizers are described in several textbooks, suchas the afore-mentioned “Digital Communications”, by John G. Proakis, 2ndedition, McGraw-Hill, New York, 1989. Also, the soft decision directedinput to the FBF, although described as the equalizer output, could be amore complex soft decision function of the equalizer output. It shouldalso be understood that the equalizer in FIG. 1 can include the trainingmode as well. The training mode of operation would be exclusive withrespect to the blind mode as in a traditional DFE and would notinterfere with the decision directed modes.

It will be understood that the equalizer design providing concurrentequalizer outputs for automatic switching and soft automatic switchingmodes is used in an exemplary embodiment and in an illustrative mannerand that it may be possible to use other arrangements to provideconcurrent outputs. Thus, while the present invention has been describedby way of exemplary embodiments, it will be recognized and understood byone of skill in the art to which the invention pertains that variouschanges and substitutions, including the foregoing described variations,may be made without departing from the invention as defined by theclaims following.

1. Mode selector apparatus for automatically selecting one of a standardautomatic switching mode and a soft automatic switching mode in adecision feedback equalizer (DFE), said mode selector apparatus beingadapted for use in a data signal processing system with equalization,said mode selector apparatus comprising: an equalizer for providingfirst and second DFE outputs corresponding to a standard decisiondirected (dd) mode and a soft dd mode, respectively; and a comparatorfor comparing byte error rates (ByER) of said first and second DFEoutputs for selecting as a superior mode that mode associated with alower ByER and outputting the DFE output with said lower ByER.
 2. Modeselector apparatus as recited in claim 1 wherein said standard automaticswitching mode selectively exhibiting a blind mode and a standarddecision directed mode and said soft automatic switching modeselectively exhibiting a blind mode and a soft dd mode.
 3. Mode selectorapparatus as recited in claim 2, including lock detector means forproviding a lock signal for indicating convergence of said DFE, saidlock signal being derived from said DFE output signal with said lowerByER.
 4. Mode selector apparatus in accordance with claim 2, whereinsaid equalizer for providing said first and second DFE output signalscomprises decision feedback equalizer means for processing said datasignal and exhibiting concurrent soft and hard decision directed outputsignals.
 5. Mode selector apparatus in accordance with claim 3, whereinsaid lock detector means includes first and second lock detectors forproviding respective lock signals derived from respective ones of saidDFE outputs.
 6. Mode selector apparatus in accordance with claim 3,including a mode switch for selectively placing said DFE outputs in oneof (a) one of said standard and soft dd modes and (b) a blind mode,depending on said lock signal identifying convergence of said DFE. 7.Mode selector apparatus in accordance with claim 3, wherein a trainingmode replaces the blind mode and including a mode switch for selectivelyplacing said DFE outputs in one of (a) one of said standard and soft ddmodes and (b) a training mode, depending on said lock signal identifyingconvergence of said DFE.
 8. Mode selector apparatus in accordance withclaim 1 further comprising: a forward error correcting processor forprocessing said first and second DFE output signals by forward errorcorrection so as to provide respective first and second forward errorcorrection (FEC) output signals; wherein: the comparator determineswhich one of said standard automatic switching mode and said softautomatic switching mode is the superior mode in accordance with adefined comparison criterion, and outputs an output signal of said onesuperior mode.
 9. Mode selector apparatus in accordance with claim 8,wherein said forward error correcting processor includes a trellisdecoder and a Reed Solomon (RS) decoder.
 10. Mode selector apparatus inaccordance with claim 9, wherein said defined comparison criterioncomprises said comparator comparing uncorrectable segment rates (USR)out of said RS decoder, selecting as a superior mode that modeassociated with a lower USR and outputting the DFE output signal withsaid lower USR.
 11. Mode selector apparatus in accordance with claim 9,wherein said defined comparison criterion comprises said comparatorcomparing estimated bit error rate out of said RS decoder, selecting asa superior mode that mode associated with a lower ByER and outputtingthe DFE output signal with said lower ByER.
 12. Mode selector apparatusin accordance with claim 1, wherein said equalizer for providing firstand second DFE output signals includes equalizer filtering means andslicer means coupled to said mode switch for providing said first andsecond DFE output signals.
 13. Mode selector apparatus in accordancewith claim 8, wherein said forward error correcting processor comprisesparallel processing means for respectively providing said first andsecond FEC output signals.
 14. Apparatus in accordance with claim 5,including a mode switch coupled to said first and second DFE outputsignals, said respective lock output signals, and to said comparator formonitoring a comparison signal for selecting one of said respective lockoutput signals to provide said lock signal, depending upon saidcomparison signal.
 15. Apparatus in accordance with claim 14, whereinsaid mode switch selects one of said respective lock output signalscorresponding to said superior mode.
 16. A method for automaticallyselecting one of a standard automatic switching mode and a softautomatic switching mode in a decision feedback equalizer (DFE) forreceiving a data signal, said method comprising the steps of: processinga received signal, including equalization and forward error correction(FEC); providing first and second DFE output signals corresponding tosaid standard automatic switching mode and said soft automatic switchingmode, respectively; processing said first and second DFE output signalsso as to provide respective first and second FEC output signals;comparing byte error rates (ByER) in each of said first and second FECoutput signals to ascertain which of said automatic switching mode andsaid soft automatic switching mode is a superior mode for ByER undergiven conditions; deriving a selection signal from said superior mode;and utilizing said selection signal for controlling said DFE.
 17. Amethod in accordance with claim 16, wherein said step of utilizing saidselection signal for controlling said DFE comprises a step of settingsaid DFE into one of (a) a blind mode, and (b) one of a standarddecision directed mode and a soft decision directed mode, depending onsaid selection signal.
 18. A method in accordance with claim 17, whereinsaid step for providing first and second DFE output signals includes: astep of equalizer filtering; and a step of signal slicing coupled forproviding said first and second DFE output signals.
 19. A method inaccordance with claim 17, wherein said step of processing said first andsecond DFE output signals comprises a step of processing said first andsecond DFE output signals in parallel paths for respectively providingsaid first and second FEC output signals.
 20. A method in accordancewith claim 17, wherein said step of FEC processing includes steps oftrellis decoding and Reed Solomon decoding.
 21. A method in accordancewith claim 16, wherein said step of utilizing said selection signal forcontrolling said DFE comprises: deriving a first lock signal from saidfirst FEC output signal; deriving a second lock signal from said secondFEC output signal; and selecting one of said first and second locksignals for controlling said DFE, depending on said selection signal.22. A method in accordance with claim 19, wherein said step ofprocessing said first and second DFE output signals comprises a step ofprocessing said data signal by a decision feedback equalizer exhibitingconcurrent soft and hard decision directed operating modes for providingsaid first and second DFE output signals.
 23. A method in accordancewith claim 22, including providing concurrently in each output symbolsoft decision bit representation concurrently both hard and softdecision representations.
 24. A method in accordance with claim 16,wherein said step of utilizing said selection signal for controllingsaid DFE comprises: deriving a lock signal from one of said first andsecond FEC output signal, depending on said selection signal; andutilizing said lock signal for controlling said DFE.
 25. A method inaccordance with claim 16, wherein said step of utilizing said selectionsignal for controlling said DFE comprises: deriving a lock signal fromthat one of said first and second FEC output signal associated with saidsuperior mode.